--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgaB1 is
  port(clk50_in  : in std_logic;
		 x   : out std_logic_vector(9 downto 0);  
		 y   : out std_logic_vector(8 downto 0);  
		 red_in   : in std_logic;
       green_in : in std_logic;
       blue_in  : in std_logic;
		 red_out   : out std_logic;
       green_out : out std_logic;
       blue_out  : out std_logic;
       hs_out    : out std_logic;
       vs_out    : out std_logic;
		 clk25_out : out std_logic;
		 inside_x : out std_logic;
		 inside_y : out std_logic);
		 
end vgaB1;

architecture behavioral of vgaB1 is

signal clk25              : std_logic;
signal hcounter : integer range 0 to 800;
signal vcounter   : integer range 0 to 521;
signal color: std_logic_vector(2 downto 0);

signal colorb: std_logic_vector(2 downto 0);
begin
    
-- generate a 25Mhz clock
process (clk50_in)
begin
  if clk50_in'event and clk50_in='1' then
    clk25 <= not clk25;
  end if;
end process;

clk25_out<=clk25;
      
---------------------------------------------------
p2: process (clk25, hcounter, vcounter)
	variable x: integer range 0 to 639;
	variable y: integer range 0 to 479;
 
begin
	-- hcounter counts from 0 to 799
	-- vcounter counts from 0 to 520
	-- x coordinate: 0 - 639 (x = hcounter - 144, i.e., hcounter -Tpw-Tbp)
	-- y coordinate: 0 - 479 (y = vcounter - 31, i.e., vcounter-Tpw-Tbp)
	x := hcounter - 144;
	y := vcounter - 31;
  	if clk25'event and clk25 = '1' then
 		-- To draw a pixel in (x0, y0), simply test if the ray trace to it
		-- and set its color to any value between 1 to 7. The following example simply sets 
		-- the whole display area to a single-color wash, which is changed every one 
		-- second. 	

	 	if x < 640 and y <      480 then
		--    	colorbv := x mod 64;  --il faut une puissance de 2 forcement pour le modulo
    	colorbv := x /64;  
			case colorbv is
				when 0 =>  colorb<= "000";
				when 1 =>  colorb<= "001";
				when 2 =>  colorb<= "010";
				when 3 =>  colorb<= "011";
				when 4 =>  colorb<= "100";
				when 5 =>  colorb<= "101";
				when 6 =>  colorb<= "110";
				when others =>  colorb<= "111";
			end case;
--				
--			with colorbv select
--				colorb<= "000" when  0,
--							"001" when  1,
--							"010" when  2,
--							"011" when  3,
--							"100" when  4,
--							"101" when  5,
--							"110" when  6,
--							"111" when  others;

			red_out <= colorb(0);
      	green_out <= colorb(1); 
      	blue_out <= colorb(2);	
    	else
			-- if not traced, set it to "black" color
      	red_out <= '0';
      	green_out <= '0';
      	blue_out <= '0';
    	end if;
		-- Here is the timing for horizontal synchronization.
		-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
	 	-- Pulse width: Tpw = 96 cycles @ 25 MHz
	 	-- Back porch: Tbp = 48 cycles
		-- Display time: Tdisp = 640 cycles
	 	-- Front porch: Tfp = 16 cycles
		-- Sync pulse time (total cycles) Ts = 800 cycles

    	if hcounter > 0 and hcounter < 97 then
      	hs_out <= '0';
    	else
      	hs_out <= '1';
    	end if;
		-- Here is the timing for vertical synchronization.
		-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
	 	-- Pulse width: Tpw = 1600 cycles (2 lines) @ 25 MHz
	 	-- Back porch: Tbp = 23200 cycles (29 lines)
		-- Display time: Tdisp = 38400 cycles (480 lines)
	 	-- Front porch: Tfp = 8000 cycles (10 lines)
		-- Sync pulse time (total cycles) Ts = 416800 cycles (521 lines)
    	if vcounter > 0 and vcounter < 3 then
      	vs_out <= '0';
    	else
      	vs_out <= '1';
    	end if;
	 	-- horizontal counts from 0 to 799
    	hcounter <= hcounter+1;
    	if hcounter = 800 then
      	vcounter <= vcounter+1;
      	hcounter <= 0;
    	end if;
	 	-- vertical counts from 0 to 519
    	if vcounter = 521 then		    
      	vcounter <= 0;
    	end if;
  end if;
end process;

end behavioral;